![]() |
|
||||||||||||||
| . 网站首页 . 产品新知 . 业界新闻 . 解决方案 . 技术文库 . 在线学院 . 活动访谈 . 下载中心 . 电子商城 . 邮购须知 . 论坛 . | ||
|
||
|
|||||
| 关于TMS320LF2407异步串行例子 | |||||
作者:TIchines… 文章来源:德州中文网 点击数: 更新时间:2006-11-28 ![]() |
|||||
|
一个关于TMS320LF2407异步串行例子:(也适用于F240) ;=========================================================== * File Name: SCI.asm * Description: PROGRAM TO PERFORM A LOOPBACK IN THE SCI MODULE * This program is capable of doing either an internal loopback or an external * loopback, depending on the value written in SCICCR. SCITXD-SCIRXD pins * should be connected together, if external loopback is desired. This is not * required for an internal loopback. The SCI receives the bit-stream and stores * the received data in memory (60h and above) for verification. * An 8 bit value is transmitted through the SCITXD pin at a baud rate of * 9600 bits/sec. A counter is used to determine how many times data is * transmitted and received. * This code is useful to determine the health of the SCI hardware quickly * without the aid of any other equipment. ;=========================================================================== .include 240x.h KICK_DOG .macro ;Watchdog reset macro LDP #00E0h SPLK #05555h, WDKEY SPLK #0AAAAh, WDKEY LDP #0h .endm ;=========================================================================== ; M A I N C O D E - starts here ;=========================================================================== .text START: LDP #0 SETC INTM ; Disable interrupts LDP #00E0h SPLK #0040h,SCSR1 ; Enable clock for SCI module SPLK #006Fh,WDCR ; Disable WD KICK_DOG SPLK #0h,60h ; Set wait state generator for: OUT 60h,WSGR ; Program Space, 0-7 wait states ;=========================================================================== ;SCI TRANSMISSION TEST - starts here ;=========================================================================== SCI: LDP #0E1h SPLK #0003h,MCRA LAR AR0, #SCITXBUF ; Load AR0 with SCI_TX_BUF address LAR AR1, #SCIRXBUF ; Load AR1 with SCI_RX_BUF address LAR AR2, #1Fh ; AR2 is the counter LAR AR3, #60h ; AR3 is the pointer LDP #SCICCR>>7 SPLK #17h, SCICCR ; 17 for internal loopback ; 07-External. For external option JP12=2-3 ; 1 stop bit,odd parity,8 char bits, ; async mode, idle-line protocol SPLK #0003h, SCICTL1 ; Enable TX, RX, internal SCICLK, ; Disable RX ERR, SLEEP, TXWAKE SPLK #0000h, SCICTL2 ; Disable RX & TX INTs SPLK #02h, SCIHBAUD SPLK #08h, SCILBAUD ; Baud Rate=9600 b/s (40 MHz SYSCLK) SPLK #0023h, SCICTL1 ; Relinquish SCI from Reset. XMIT_CHAR: LACL #61h ; Load ACC with xmit character MAR *,AR0 SACL *,AR1 ; Write xmit char to TX buffer XMIT_RDY: BIT SCICTL2,BIT7 ; Test TXRDY bit BCND XMIT_RDY,NTC ; If TXRDY=0,then repeat loop RCV_RDY: BIT SCIRXST,BIT6 ; Test RXRDY bit BCND RCV_RDY,NTC ; If RXRDY=0,then repeat loop READ_CHR: LACL *,AR3 ; The received (echoed) character is ; stored in 60h SACL *+,AR2 ; This loop is executed 20h times BANZ XMIT_CHAR ; Repeat the loop again LOOP B LOOP ; Program idles here after executing ; transmit loops .end |
|||||
| 欢迎点击进入:"61IC中国电子在线"官方网站 文章录入:admin 责任编辑:admin | |||||
| 【发表评论】【加入收藏】【告诉好友】【打印此文】【关闭窗口】 | |||||
| 最新热点 | 最新推荐 | 相关文章 | ||
| F2812开发板:2812EVM-III开发 用来测试TI公司TMS320F281X芯 利用汇编语言进行F2812编程实 利用汇编语言进行F2812编程实 利用汇编语言进行F2812编程实 利用汇编语言进行F2812编程实 利用汇编语言进行F2812编程实 利用汇编语言进行F2812编程实 利用汇编语言进行F2812编程实 FFT 快速傅立叶变换 (c语言) |
| 网友评论:(只显示最新10条。评论内容只代表网友观点,与本站立场无关!) |
| | 设为首页 | 加入收藏 | 联系站长 | 友情链接 | 版权申明 | 网站公告 | 管理登录 | | |||
|