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*************************************************************************
***
*** VC5402 Bootloader Software : Version 1.03
*** Origin Date : 9/30/98
*** Author(s) : RDP
***
*************************************************************************
***
*** This code sets up and executes the VC5402 Bootloader.
***
*** Revision History:
*** ----------------
*** 1.00 Modified the VC5410 bootloader for use RDP 09/30/98
*** on the VC5402. Added new HPI boot mode,
*** and removed McBSP2 code. See notes on
*** HPI boot mode below.
*** 1.01 Fixed bug in 8bit parallel mode, by RDP 11/12/98
*** masking off the upper ACCUA bits of
*** the word containing the upper byte
*** of the section size.
*** 1.02 Fixed the 8bit standard serial mode, RDP 02/26/99
*** by changing the initialization of RCR11
*** and XCR11 from 040h to 0h.
*** Added a SPI EEPROM bootmode, which is
*** selected via the INT3 flag (See notes
*** on SPI boot mode below). Changed the
*** references to the McBSP control
*** registers to emphasize the sub-bank
*** addressing scheme. Added more comments,
*** and cleaned-up spacing on older code.
*** Fixed a bug in 8-bit I/O mode, by loading
*** the top of B with zero. Added code to
*** toggle the BDX1 pin during init, to
*** provide a high-to-low transition that
*** can be used to drive INT3 for selection
*** of the SPI boot mode.
*** 1.03 Modified Parallel 8-bit. PMJ2 12/06/99
*** Modified I/O 8-bit boot modes.
*** In the parallel 8-bit mode, the AG and AH
*** are forced to zero for correct evaluation.
*** In the 8-bit I/O mode, the XPC
*** destination addr is correclty saved.
*** The BG and BH are forced to zero
*** for correct evaluation. The SPI mode boot
*** branches to the parallel boot after failure
*** of the first condition (08) and second condition (AA).
*** Reset McBSP1 before DX pins toggles. (for debugging)
***
*************************************************************************
*** --------------- Notes on '5402 HPI Boot Mode ---------------
*** The new HPI boot mode allows the host to load the on-chip RAM
*** after the '5402 is reset. The boot-mode also allows the host
*** to specify an entry point at load-time. After completing the
*** bootload process, the host must make another HPI access to load
*** the entry point to location 07Fh of on-chip RAM. This is how it
*** works: after reset, the bootloader initializes address 07Fh to
*** zero, then polls this location for a change while the host is
*** loading the code. When the bootloader detects a change in the
*** contents of address 07Fh, it performs a branch using the contents
*** as the destination address.
*** This new mode doesn't require the INT2 flag for selection. If the
*** INT2 pin is not used to select HPI boot mode, the bootloader
*** periodically checks various boot sources, including HPI, until a
*** boot condition is detected. Alternatively, the INT2 flag can be
*** used to force the bootloader to ignore all boot sources other
*** than HPI. If the INT2 flag is to be used, a high to low transition
*** is required on the INT2 pin within 30 cycles after the '5402 is
*** reset.
*************************************************************************
*** --------------- Notes on '5402 SPI Boot Mode ---------------
*** The SPI boot mode allows the '5402 to boot from an 8-bit serial
*** EEPROM using the SPI protocol. The mode is selected at reset via
*** the INT3 external interrupt . Proper selection of the boot mode
*** requires a high to low transition on the INT3 pin within 30 CPU
*** cycles after the '5402 is reset.
***
*** The EEPROM must be connected to McBSP1 as follows:
*** McBSP1 EEPROM
*** ****** ******
*** BCLKX SCK
*** BFSX /CS
*** BDX SI
*** BDR SO
*** XF /HOLD (Optional - disables EEPROM when done)
***
*** The boot table used for programming the EEPROM is generated
*** using the 8bit serial option of the Hex conversion utility.
*** example:
*** -bootorg SERIAL
*** -memwidth 8
*************************************************************************
.title "bootVC5402"
.mmregs
.version 548
.def boot
.def endboot
.def bootend
.def dest
.def src
.def lngth
.def hbyte
.ref SPI_INIT, SPI_READ, SPI_WRITE
.ref SPI_RDSR, SPI_WRSR
*************************************
pa0 .set 0H ; port address 0h for i/o boot load
xentry .set 61H ; XPC of entry point
entry .set 62H ; entry point
hbyte .set 63H ; high byte of 8-bit serial word
p8word .set 64H ; concatenator for 8-bit memory load
src .set 65H ; source address
dest .set 66H ; destination address (dmov from above)
xdest .set 67H ; XPC of destination address.
lngth .set 68H ; code length
temp0 .set 69H ; temporary register0
temp1 .set 6aH ; temporary register1
temp2 .set 6bH ; temporary register2
temp3 .set 6cH ; temporary register3
HPIentry .set 7Fh ; Entry point for HPI boot.
***********************************************
* MMR definition for c54xlp peripherals *
*------------- MCBSP0 ----------------------*
drr10 .set 21H ; Data Receive Register
dxr10 .set 23H ; Data Transmit Register
SPSA0 .set 0038H ; Serial Port 0 Sub-bank Address Register
SPSD0 .set 0039H ; Serial Port 0 Sub-bank Data Register
*------------- MCBSP1 ----------------------*
drr11 .set 41H ; Data Receive Register
dxr11 .set 43H ; Data Transmit Register
SPSA1 .set 0048H ; Serial Port 1 Sub-bank Address Register
SPSD1 .set 0049H ; Serial Port 1 Sub-bank Data Register
*----------- MCBSP CONTROL REGS --------------*
SPCR1_SUBADDR .set 0000H ; Serial Port Control Register 1 (subaddress)
SPCR2_SUBADDR .set 0001H ; Serial Port 1 Control Register 2 (subaddress)
RCR1_SUBADDR .set 0002H ; Receive Control Register 1 (subaddress)
RCR2_SUBADDR .set 0003H ; Receive Control Register 2 (subaddress)
XCR1_SUBADDR .set 0004H ; Transmit Control Register 1 (subaddress)
XCR2_SUBADDR .set 0005H ; Transmit Control Register 2 (subaddress)
SRGR1_SUBADDR .set 0006H ; Sample Rate Genarator Register 1 (subaddress)
SRGR2_SUBADDR .set 0007H ; Sample Rate Genarator Register 2 (subaddress)
PCR_SUBADDR .set 000EH ; Pin Control Register (subaddress)
*-------------- Other contants ---------------*
int2msk .set 0004H ; INT2_ bit position on IFR
int3msk .set 0100H ; INT3_ bit position in IFR/IMR
**********************************************************
* bootloader
**********************************************************
.sect "boot"
boot
ssbx intm ; disable all interrupts
stm #0FFFFh,@ifr ; clear IFR flag
ld #0, dp
orm #02b00h, @st1 ; xf=1, hm=0, intm=1, ovm=1, sxm=1
orm #020h, @pmst ; ovly=1
stm #07fffh, swwsr ; 7 wait states for P_,D_, and I_ spaces
stm #0007dh, sp ; Use top part of scratch-pad RAM for stack.
*****************************************************************
* RDP, Modified old HPI boot check to support host loading
* after reset. Initialize HPI boot entry point to 0. The host
* will change the value of this location after loading RAM.
*****************************************************************
stm #0, @HPIentry ; Set HPI entry to known value.
stm #08h, hpic ; Set HINT pin low. Ok to start
; host load.
*****************************************************************
* Toggling the BDX pin on McBSP1. This pin can be used to
* drive /INT3 and select the SPI boot mode, without requiring
* an external signal.
*****************************************************************
STM SPCR2_SUBADDR,SPSA1
STM #0000h,SPSD1 ; DISABLES TRANSMIT. (reset) 1.03
stm #PCR_SUBADDR, SPSA1
stm #02020h, SPSD1 ; Set DX high.
rpt #5 ; Keep high a while.
nop
stm #02000h, SPSD1 ; Set DX low.
rpt #5 ; wait several cycles
nop ; before checking INT2
bitf @ifr, #int2msk ; Check if INT2_ flag is set
nop
bc HPI, tc ; If int2 is set then HPI boot.
bitf @ifr, #int3msk ; Else, check if INT3_ flag is set
nop
bc SPIBOOT, tc ; If int3 is set then SPI boot.
b parallel ; Otherwise, check other boot modes.
*****************************************************************
* HPI boot mode selected through int2.
*****************************************************************
HPI ; Else, this is an HPI boot, all
; other boot modes are ignored.
stm #int2msk, ifr ; Clear INT2_ bit in ifr.
ldm HPIentry, a ; Get HPI entry vector.
bc hpiboot, aneq ; If not zero, HPI boot.
b $-3 ; else, keep looping.
*****************************************************************
* Check Parallel Boot
*****************************************************************
parallel
stm #0h, @xentry ; initialize the entry point
stm #boot, @entry ;
portr #0ffffh, @src ; read source address of boot table
mvdk @src, ar1 ; ar1 points at source memory (Data)
ld *ar1+, a ; load accumulator A with BRW
sub #10AAh, a, b ; check 16-bit Boot?
bc par16, beq ; a=010AAh
and #0ffh, a ; check acc AL = 08
sub #8h, a, b ; check 8-bit Boot?
bc chk_data, bneq ; a=08xxh
ld *ar1+, a ; 8-bit mode, LSB
and #0ffh, a ; check acc AL = AAh
sub #0AAh, a ; LSB = 0AAh?
bc par08, aeq ; 8-bit Parallel Boot
chk_data stm #0FFFFh, ar1 ; check data memory 0xFFFF
nop ; prevent pipeline conflict
nop ;
ld *ar1+, a ; load accumulator A with BRW
stlm a, ar1 ; ar1 point at source memory (Data)
nop ; prevent posibble pipeline conflic
nop ;
ld *ar1+, a ; load acculator A with BRW
sub #10AAh, a, b ; check 16-bit Boot?
bc par16, beq ; a=010AAh
stm #0FFFFh, ar1 ; check data memory 0xFFFF & 0xFFFE
nop ; prevent possible pipeline conflic
nop ;
ldu *ar1-, a ; acc A <-- source address
and #0FFh, a ; 0 the high byte
add *ar1, 8, a ;
stlm a, ar1 ;
nop ; prvent possible pipeline conflic
nop ;
ld *ar1+, a ; load accumulator A with BRW
and #0ffh, a ; check acc AL = 08h
sub #8h, a, b ; check 8-bit Boot?
bc ser_ini, bneq ; acc A = 08xxh
ld *ar1+, a ; 8-bit mode, LSB
and #0ffh, a ; check acc AL = AAh
sub #0AAh, a ; LSB = 0AAh?
bc par08, aeq ; 8-bit Parallel Boot
ser_ini
********************************************************************************
*
* Initialization for 5402 BSPs
*
********************************************************************************
*
* 1. BSP0 is configured for 16-bit, BCLKX input, BFSX input.
*
********************************************************************************
*
STM SPCR1_SUBADDR,SPSA0
STM #0000h,SPSD0 ; DISABLES RECEIVE.
STM SPCR2_SUBADDR,SPSA0
STM #0000h,SPSD0 ; DISABLES TRANSMIT.
STM RCR1_SUBADDR,SPSA0 ; Set the receive word length to 16-bit.
STM #0040H,SPSD0
STM RCR2_SUBADDR,SPSA0 ; Set the receive word length to 16-bit.
STM #0041H,SPSD0 ; Single Phase, 16-bit, No Compan,1bit Delay.
STM SRGR1_SUBADDR,SPSA0
STM #0000H,SPSD0 ; Clear the clkdiv and frame width.
STM SRGR2_SUBADDR,SPSA0
STM #0000H,SPSD0 ; Clksm=0 External source.
STM PCR_SUBADDR,SPSA0
STM #0000H,SPSD0 ; BCLKX and FSX configured as inputs
STM SPCR1_SUBADDR,SPSA0
STM #0001H,SPSD0 ; ENABLES RECEIVE.
********************************************************************************
* 2. BSP1 is configured for 8-bit, clk input, fm input. *
********************************************************************************
STM SPCR1_SUBADDR,SPSA1
STM #0000h,SPSD1 ; DISABLES RECEIVE.
STM SPCR2_SUBADDR,SPSA1
STM #0000h,SPSD1 ; DISABLES TRANSMIT.
STM RCR1_SUBADDR,SPSA1 ; Set the receive word length to 8-bit.
STM #0000H,SPSD1
STM RCR2_SUBADDR,SPSA1 ; Set the receive word length to 8-bit.
STM #0001H,SPSD1 ; Single Phase, 8-bit, No Compan,1bit Delay
STM SRGR1_SUBADDR,SPSA1
STM #0000H,SPSD1 ; Clear the clkdiv and frame width.
STM SRGR2_SUBADDR,SPSA1
STM #0000H,SPSD1 ; Clksm=0 External source.
STM PCR_SUBADDR,SPSA1
STM #0000H,SPSD1 ; BCLKX and FSX configured as inputs
STM SPCR1_SUBADDR,SPSA1
STM #0001H,SPSD1 ; ENABLES RECEIVE.
********************************************************************************
***
rsbx xf ; signal ready-to-receive
chk_ser bitf ifr, #400h ; check RINT1 flag
cc BSP1, tc ;
bitf ifr, #10h ; check RINT0 flag
cc BSP0, tc ;
bc pasyini, bio ; check for I/O boot
**************RDP***************
* Add HPI entry check here. *
********************************
ldm HPIentry, a ; Get HPI entry vector.
bc hpiboot, aneq ; If not zero, HPI boot.
b chk_ser ; else, keep looping.
********************************
*****************************************************************
* End-boot, simply branch to source address
*****************************************************************
endboot
ldu @entry,a ; branch to the entry point
add @xentry,16,a ;
hpiboot fbacc a
*****************************************************************
* Bootload from 8-bit memory, MS byte first
*****************************************************************
par08
ld *ar1+, 8, a ; read MSB of SWWSR value
mvdk *ar1+, ar3 ; read LSB of SWWSR value
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stlm a,swwsr ; store A to SWWSR
ld *ar1+, 8, a ; read MSB of BSCR value
mvdk *ar1+, ar3 ; read LSB of BSCR value
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stlm a,bscr ; store A to BSCR
ld *ar1+, 8, a ; read MSB of XPC of entry addr
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stl a,@xentry ; stor A to xentry
ld *ar1+, 8, a ; read MSB of entry address
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stl a,@entry ; stor A to entry
par08_1 ld *ar1+, 8, a ; get MSB of block size (16-bit words)
and #0ff00h, a ; Clear grd bits, and upper word. Rev1.01
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
bcd endboot,aeq ; section size =0 indicate boot end
sub #1,a,b ; brc = section size - 1
stlm b, brc ; update block repeat counter register
ld *ar1+, 8, a ; get MSB of XPC of destination
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stl a,@dest ; @dest <-- XPC
ld *ar1+, 8, a ; get MSB of destinationaddress
************* Bug fix ******************************************************
and #0ff00h,a ;force AG, AH to zero for correct calculation
;of the 23-bit destination address.
;(11/10/99 PMJ2) 1.03
****************************************************************************
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
add @dest,16,a ; acc A <-- 23-bit destination address
rptb xfr08-1
ld *ar1+, 8, b ; read MSB of data
mvdk *ar1+, ar3 ; read LSB of data
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, b ; Concatenate
rpt #10 ;insert at least 10 cycles
nop ; between read and write
writa BL ; write object data to destination
add #1, a ; increment destination address
xfr08
b par08_1
*****************************************************************
* Bootload from 16-bit memory
*****************************************************************
par16
ld *ar1+, a ; read desired value of SWWSR
stlm a, @swwsr ; store in SWWSR
ld *ar1+, a ; read desired value of BSCR
and #0FFFEh,a ; ensure EXIO bit is off
stlm a, @bscr ; store in BSCR
ld *ar1+, a ; read XPC of entry point address
stl a, @xentry ; and store
ld *ar1+, a ; read low 16-bits of entry point addr
stl a, @entry ; and store
par16_1 ld *ar1+,a ; load the size of section to A
bcd endboot,aeq ; section size =0 indicate boot end
sub #1,a,b ; brc = section size - 1
stlm b, brc ; update BRC
ld *ar1+,a ; get the XPC of destination (A22-A16)
stl a,@dest ; store XPC at data memory @dest
ldu *ar1+,a ; get address of destination in A(15-0)
stlm a,ar2 ; store dest address at ar2
add @dest,16,a ; acc A <--- 23-bit destination address
rptb xfr16-1
mvdk *ar1+, ar3 ; read object data
rpt #10 ;insert at least 10 cycles
nop ; between read and write
writa @ar3 ; write object data to destination
add #1,a ;increment desintation address
xfr16
b par16_1
*****************************************************************
* Bootload from BSP serial port
*****************************************************************
ser_in
rsbx tc ; clear flag
bcd $, ntc ; begin receive data routine
BITF *AR6,#0002h ; Bit test on RRDY. Reception of a new word.
RET
BSP0
STM SPCR1_SUBADDR,SPSA0 ; Set up to read the value of the
STM SPSD0,AR6 ; SPCR10 reg, RRDY.
stm #drr10,ar1 ; ar1 <-- drr0
stm #010h, @ifr ; clear BRINT0 flag
b SP_in_16 ; check BSP
BSP1
STM SPCR1_SUBADDR,SPSA1 ; Set up to read the value of the
STM SPSD1,AR6 ; SPCR10 reg, RRDY.
stm #drr11,ar1 ; ar1 <-- drr0
stm #400h, @ifr ; clear BRINT1 flag
b SP_in_8 ; check BSP
*****************************************************************
* McBSP Bootload in 16-bit mode *
*****************************************************************
SP_in_16
ldm *ar1, a ; acc A <-- DRR
sub #10AAh, a, b ; acc A = 0x10AA ?
bc ser_in_16, beq ; 16-bit serial mode
ret
ser_in_16
;The dummy words are read to maintain
&n
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